1. Field of the Invention
The present invention generally relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device with an improved structure suitable for wafer voltage control and with reliable operation of field effect transistors.
2. Description of the Related Art
In recent years and continuing, a technique for dynamically controlling the threshold voltage of a transistor to reduce power consumption caused by leakage current is attracting attention.
The lower the threshold voltage of a transistor, the higher the operating speed is. However, with lower threshold voltage, subthreshold leakage current involved in the ON/OFF switching operation increases, and consequently the power consumption increases. In contrast, if the threshold voltage is high, subthreshold current leakage decreases although the performance is degraded.
Making use of this feature, the threshold voltage is dynamically controlled by software so as to be at a lower level when high-speed operation is required and at a higher level if not.
It is known that the threshold voltage can be changed by controlling the wafer voltage of a transistor. See, for example, 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 88-89, 2004 (Publication 1). However, it is difficult in fact to appropriately regulate the wafer voltage while maintaining the electric current characteristics of nanoscale transistors. As the gate length is narrowed, the source and drain diffusion layers get closer and interfere with each other, and the intended level of voltage cannot be acquired directly below the channel even though a wafer voltage of a designed level is applied. Thus, desired change in characteristics cannot be achieved.
Meanwhile, to prevent lateral diffusion of the source and drain regions, it is proposed to form a diffusion preventing amorphous layer in a part of the surface area directly below the sidewall spacers located on both sides of the gate electrode. See JP 2005-136351A (Publication 2).
FIG. 1 is a schematic diagram for illustrating a prior art technique for preventing lateral diffusion of the source and drain regions disclosed in Publication 2. A gate electrode 102 is formed via a gate insulator 109 on a semiconductor substrate 101. Extension regions 103 are formed by ion implantation using the gate electrode 102 as a mask. The first sidewall spacers 104 are formed, and diffusion preventing amorphous layers 106 are formed by implanting ions having an impurity diffusion preventing function (such as nitrogen (N), fluorine (F), or carbon (C)) using the gate electrode 102 and the first sidewall spacers 104 as masks, and by making the impurity-implanted layers in alignment with the first sidewall spacers 104 uncrystallized. Then, the second sidewall spacers 107 are formed. The source/drain regions 105 are formed by ion implantation using the gate electrode 102, the first sidewall spacers 104 and the second sidewall spacers 107 as masks.
The technique disclosed in Publication 2 is directed to prevent lateral diffusion of the source/drain regions by amorphous layers, and irrelevant to control of bias voltage applied to a wafer. Simple application of this technique to wafer voltage control cannot prevent dopants and impurities from migrating to the channel 110 passing beneath the diffusion preventing layer 106 although lateral diffusion of impurities may be prevented. As a result, interference occurs between the source and the drain, which interference adversely affects the wafer voltage being applied.
It may be proposed to control the width of the second sidewall spacer 107 to the optimum width in order to improve the effect of wafer bias voltage. By adjusting the width of the second sidewall spacer 107, the distance from the channel 110 to the source/drain regions 105 is increased and interference may be reduced; however, another problem occurs. That is, the ON-current decreases due to the increased distance between the channel and the source/drain regions 105.